1. Field of the Invention
This invention relates generally to a method of determining the frequency of a clock signal, and, more particularly, to a method of first determining the actual frequency of an inaccurate clock signal by counting the number of clock pulses of the clock signal during a specified amount of time and then determining a compensation factor based on the actual frequency to be used as a correction of the rated frequency of the clock signal for a particular digital circuit timing application.
2. Discussion of the Related Art
As is well understood, all digital circuits use one or more clock signals for digital logic timing purposes. These clock signals can be generated by different types of devices, such as various crystals, resonators, etc. The different clock signal generating devices can provide a wide range of different clock signal frequencies at varying degrees of accuracy. The accuracy of the clock signal is determined by the ability of the device to generate a particular frequency at any particular time within a certain percent error. Depending on the particular clock signal source, temperature, age, etc. have an effect on its output frequency and accuracy. Clock signal generating devices that are more accurate and maintain their accuracy over time at varying temperatures are generally more expensive.
A powertrain control module (PCM) incorporating digital logic circuitry is provided in modern day vehicles having internal combustion engines to control the operation of the engine and transmission functions of the vehicle. The PCM controls the timing of the application of fuel and ignition spark to the various cylinders of the engine to provide spark dwell and placement and fuel pulse-width and placement. Additionally, the timing signal provides communication protocol bit timing. To generate the timing signals necessary to provide this control, the PCM utilizes a high frequency system clock (having a frequency, for example, of 20 MHZ) and a low frequency control clock (having a frequency, for example, of 2 MHZ). The high frequency system clock is often a low-frequency crystal (for example 32 KHz) which is multiplied to a much higher frequency within the CPU. The low frequency control clock is typically a resonator in this type of application. The relatively fast system clock is necessary to meet the high data rate demands for processing the lines of microcode in the PCM, and the slower control clock is necessary to provide appropriate timing for the output signals for the fuel and ignition sparks.
The currently used high frequency system clock has a long term frequency that is generally predictable and stable (.+-.0.1%) over temperature and age, but has short term "jitter" that can make one pulse width significantly vary from another pulse width or from its expected pulse width. This jitter is caused by the multiplying of the low frequency crystal within the CPU. The lower frequency control clock typically does not have short term jitter, but has a relatively high long term error (.+-.2.0%), and thus has significant drift as a result of age and temperature variances. The relatively inaccurate control clock signal is acceptable for misfire detection, but is unacceptable for other purposes, such as force motor pulse-width modulation. Additionally, the jitter on the high frequency system clock signal could make the fuel and ignition control signals inaccurate leading to higher emissions and/or lower fuel economy and failures to comply with requirements.
FIG. 1 shows a series of clock signals on lines A-F that illustrate the signals discussed above. Line A represents a high frequency system clock signal having a certain period, where the long term average frequency of the system clock signal is highly accurate, but short term jitter makes the individual pulses inaccurate relative to each other. Line B represents a low frequency control clock signal where the individual clock pulses are stable relative to each other, but the long term clock frequency may be relatively inaccurate. Line C shows an output control signal having a desired pulse width, that is used for example to provide fuel and ignition spark timing in an internal combustion engine. Because of the jitter in the system clock signal, the actual clock pulse width of the output signal generated from the system clock signal could fall at a number of locations, as represented by the output signal in line D. This makes the system clock not practical to be used as a timing signal for the output signals that control fuel and ignition sparks on some applications with higher resolution and accuracy requirements.
The currently existing resonators that generate the control clock signals in a PCM have been inexpensive resonators, and their long term accuracy, as discussed above, has effected the accuracy of the fuel and ignition control output signals. To illustrate this, line E represents an output control signal that is based on a control clock signal that has too high of a frequency, and line F represents an output signal that is based on a control clock signal that has too low of a frequency for the desired output signal. With the new requirements and clock jitter, there is a significant margin of error at which the ignition and spark are applied to the cylinders in the prior art PCMs.
Industry standards establish the accuracy of the control clock signal to provide the precision of when the fuel and ignition signals are applied. As the sophistication and performance requirements of modern vehicles increases, the accuracy at which the fuel and ignition spark are controlled becomes more critical, and thus the accuracy of the control clock becomes increasingly more important. More accurate resonators can be provided in the PCM to generate more accurate control clock signals or the resonator can be replaced with crystals, however, these resonators and crystals become increasingly more expensive as their accuracy increases.
What is needed is a technique for determining the frequency of a relatively inaccurate clock signal, and providing compensation of the clock signal once it is determined, so as to eliminate the need for a more accurate clock generating device. It is therefore an object of the present invention to provide such a technique.